1. Field
The present invention relates generally to voltage regulators and, more particularly, to low dropout regulators.
2. Description of Related Art
Low dropout (LDO) voltage regulators are distinguished from more traditional regulators by their ability to maintain regulation even when there are only small differences between a supply voltage and a load voltage. Thus, “dropout voltage” refers to the difference between the output voltage and the input voltage at which the circuit quits regulation.
Related LDOs may have either an NMOS output transistor or a PMOS output transistor which may be selected based on a number of design considerations. In particular, FIG. 1 depicts a related LDO having an NMOS output transistor. A differential input stage 104 controls two current sources 106, 108 that, respectively, in turn control the gate of the output transistor 114 through a PMOS source-follower 112. A compensation capacitor 110 establishes an internal pole that helps ensure the gain drops low enough before any other internal or external poles are reached thereby assisting in the circuit's stability. The differential input stage 104 includes as its inputs a reference voltage 102 and a feedback signal 124 from between voltage divider resistors 116 and 118. The regulated output voltage 120 drives a load 122 that may include an output capacitor.
In operation, a voltage glitch of the reference voltage 102 may cause an increase of the output voltage. When the glitch goes away, the output voltage also is supposed to return to normal but what may happen is that the control loop will turn off the NMOS output transistor. Because the output capacitor may have a large capacitance, it takes a relatively long time to drain any extra charge when the load current is small. During this relatively long period of time the internal compensation node will also discharge until reaching a ground state.
If, however, another load is applied during this period, it will take time to charge the internal compensation capacitor 110 before the gate of the output transistor 114 is driven high enough to drive an output. In other words, the internal compensation node will have to swing from ground to VOUT 120 which will take time especially if the compensation capacitor 110 is relatively large and the current source is low. This behavior is undesirable and disadvantageous.
Accordingly, there remains an unfilled need in this technology for improvements to LDOs that maximize load transient response times without disadvantageous design choices.